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| ZL50212 288 Channel Voice Echo Canceller Data Sheet Features * ZL5012 has nine Echo Voice Processors in a single BGA package. This single device provides 288 channels of 64 msec echo cancellation or 144 channels at 128 msec echo cancellation Each Echo Voice Processor has the capability of cancelling echo over 32 channels Each Echo Voice Processor (EVP) shares the address bus and data bus with each other Fully compliant to ITU-T G.165, G.168 (2000) and (2002) specifications Passed all AT&T voice quality tests for carrier grade echo canceller The ZL5012 provides more than 63% board space savings when compared with the nine Echo Voice Processors packaged devices Each EVP has a Patented Advanced Non-Linear Processor with high quality subjective performance Each EVP has protection against narrow band signal divergence and instability in high echo environments Each EVP can be programmed independently in any mode e.g. Back-to-Back or Extended Delay to provide capability of cancelling different echo tails. Each EVP has 0 to -12 dB level adjusters at all signal ports (Rin, Sin, Sout and Rout) Each EVP has the same JTAG identification code Ordering Information ZL50212GB 535 - Ball BGA -40C to +85C March 2003 * * * * * Applications * * * * * * Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer system Description The ZL5012 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The ZL5012 architecture contains 144 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 288 channels of 64 milliseconds to 144 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The ZL5012 supports ITU-T G.165 and G.164 tone disable requirements. * * * * * ZL5012GB Rin1...Rin9 Rout1..Rout9 Sin1....Sin9 D0....D7 CS1..CS9 A0..A12 EVP1 EVP2 EVP3 Sout1..Sout9 EVP4 EVP9 EVP5 IRQ1..IRQ9 RESET1..RESET9 EVP6 EVP7 EVP8 DTA1..DTA9 MLCK Fsel R/W ODE C4i Figure 1 - ZL5012 Device Overview Foi DS 1 ZL50212 Data Sheet VDD1 (3.3V) VSS VDD2 (1.8V) ODE Echo Canceller Pool Rin Sin MCLK Fsel PLL Serial to Parallel Group 0 ECA/ECB Group 1 ECA/ECB Group 2 ECA/ECB Group 3 ECA/ECB Parallel to Serial Rout Sout Group 4 ECA/ECB Group 5 ECA/ECB Group 6 ECA/ECB Group 7 ECA/ECB Group 8 ECA/ECB Group 9 ECA/ECB Group 10 ECA/ECB Group 11 ECA/ECB Group 12 ECA/ECB C4i F0i Timing Unit Group 13 ECA/ECB Group 14 ECA/ECB Group 15 ECA/ECB Note: Refer to Figure 4 for EVP block diagram IC0 RESET Microprocessor Interface Test Port DS CS R/W A12-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST Figure 2 - Single Echo Voice Processor (EVP) Overview Features of Echo Voice Processor (EVP) * * * * * * * * * * * * * * * * * * Each EVP can cancel echo tails of 64ms (32 channels) to 128ms (16 channels) with the ability to mix channels at 128ms or 64ms in any combination Independent Power Down mode for each group of 2 channels for power management Fully compliant to ITU-T G.165, G.168 (2000) and (2002) specifications Passed all AT&T voice quality tests for carrier grade echo canceller Compatible to ST-BUS and GCI interface at 2Mb/s serial PCM PCM coding, /A-Law ITU-T G.711 or sign magnitude Per channel Fax/Modem G.164 2100Hz or G.165 2100Hz phase reversal Tone Disable Per channel echo canceller parameters control Transparent data transfer and mute Fast reconvergence on echo path changes Fully programmable convergence speeds Patented Advanced Non-Linear Processor with high quality subjective performance Protection against narrow band signal divergence and instability in high echo environments 0 dB to -12 dB level adjusters (3 dB steps) at all signal ports Offset nulling of all PCM channels 10 MHz or 20 MHz master clock operation 3.3 V pads and 1.8V Logic core operation with 5-Volt tolerant inputs IEEE-1149.1 (JTAG) Test Access Port 2 Zarlink Semiconductor Inc. Data Sheet 1 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ZL50212 29 30 A B C D E F G ZL5012GB BGA BALL GRID ARRAY H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 29 30 Figure 3 - 535 Ball BGA Ball Grid Array Zarlink Semiconductor Inc. 3 ZL50212 Pin Description Signal Name VDD1 = 3.3V (VDD_IO) Signal Type Power BGA Ball # Data Sheet Signal Description AC5,AC26,AC27,AD26,AD5,AE5,AF12,AF13,AF1 Positive Power Supply. 4,AF17,AF18,AF19,AF24,AF6,AF7,AF8,AG24,AH Nominally 3.3 volt ( I/O 24,E13,E14,E17,E18,E19,E23,E24,E25,E6,E7,E8, voltage). F5,G26,G27,G5,H26,H5,M26,M5,N26,N5,P26,P27 , P4,P5,U26,U27,U4,U5,V26,V5,W26,W5 AA26,AA28,AA3,AA5,AB26,AB28,AB3,AB5,AF11, Positive Power Supply. AF20,AG10,AG21,AG22,AH10,AH11,AH22,AJ15, Nominally 1.8 volt (Core AJ16,AJ9,AK9,C10,C11,C22,C23,C9,D10,D23,D9, voltage). E11,E20,E21,E22,J26,J27,J4,J5,K26,K27,K3,K5, L26,L27,L3,L5,Y26, Y27,Y3,Y5 A29,A30,AF5,AG15,AG16,AG26,AG27,AG4,AH15 Ground , AH16,AH21,AH28,AH3,AJ2,AJ21,AJ29,AK1,AK30, B1,B15,B16,B2,B29,C15,C16,C28,C3,D15,D16, D27,D4,E26,E5,N13,N14,N15,N16,N17,N18,P13, P14,P15,P16,P17,P18,R13,R14,R15,R16,R17, R18,R2,R27,R28,R29,R3,R4,T13,T14,T15,T16, T17,T18,T2,T27,T28,T29,T3,T4,U13,U14,U15, U16,U17,U18,V13,V14,V15,V16, V17,V18 TEST PINS VDD2 = 1.8V (VDD_Core) Power VSS Power TE1, TE2, TE3, TE4, TE5, TE6, TE7, TE8, TE9 M4,AK26,M3,AJ4,AK4,AK25,K30,N28,AJ14 Test Mode Pins Internal Connection. Connected to VSS for normal operation. OUTPUT TEST PINS Test pins No connection. These D8,P28,C12,AK10,AH12,AD29,H28,J29,AC28, D12,P29,E9,AJ11,AK11,AD30,G28,H29,AB27,A3, pins must be left open for normal operation. P2,A2,Y1,AA1,AJ17,C20,B21,AK17,B3,P1,D3, AA2,AB1,AK18,B22,D21,AJ18,C2,R1,E3,AB2, AB4,AH18,D19,A22,AK19,D2,T1,E4,AC1,AC2, AG18,A21,B20,AJ19,C1,U1,F4,AC4,AD1,AK20, C19,A20,AH19,F3,U2,E2,AC3,AD2,AK21,B19, A19,AG19,E10,P30,B12,AJ12,AG13,AC29,J30, G29,AC30,A11,N30,D11,AH13,AK12,AB29,H30, G30,AB30,A10,N27,B11,AJ13,AG14,AA27,F29, F30,AA29,A9,A14,B10,AG11,AG12,Y28,E29,E28, AA30,A8,A13,B9,AJ10,AF10,Y29,D29,E30,Y30, C8,B14,B8,AG9,AH9,W28,D26,D28,W29,C4, E12,C5,AA4,Y4,R30,A23,B23, T30,B4,P3,A4,Y2,W1,AG17,D20,C21,AH17 4 Zarlink Semiconductor Inc. Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # ZL50212 Signal Description Internal Connection. Connected to VSS for normal operation. INPUT TEST PINS A27,D5,A25,A26,A24,B24,A28 SC_EN, SC_FCLK, SC_IN, SC_M_MCLK, SC_RESET, SC_SET, SC_T_MCLK, Halt Step C14, D14 THalt and TStep Internal Connection. Connected to VSS for normal operation. Signal Name Signal Type BGA Ball # USER SIGNAL PINS Signal Description D0, D1, D2, D3, D4, D5, D6, D7 A0,A1,A2,A3,A4,A5, A6,A7, A8, A9, A10,A11,A12 User Signals User Signals AK7,AJ8,AK8, Data Bus D0 to D7 (Bidirectional). These pins form AJ27,AK29,AJ28, the 8-bit bidirectional data bus of the microprocessor port. They are connected to all the EVP's. AH27, AJ30 Address A0 to A12 (Input). These inputs provide the AG28,AH29, AH30,AG29,AF28, A12 - A0 address lines to the internal registers. They AG30,AE28,AF29, are connected to all the EVP's. AE29,AF30,AD27, AE30,AD28 R5,L28,T5,AF15, AF16,E16,T26, R26,E15 Chip Select (Input). These active low inputs are used to enable the microprocessor interface of each EVP . CS1,CS2,CS3, CS4, CS5, CS6, CS7, CS8, CS9 User Signals RESET1 RESET2, RESET3, RESET4, RESET5, RESET6, RESET7, RESET8, RESET9 User Signals EVP Reset (Schmitt Trigger Input). An active low resets the device and puts the Voice Processor into a M2,AH23,M1,AH5, low-power stand-by mode. When the RESET pin is AJ5,AJ23,N29, returned to logic high and a clock is applied to the MCLK pin, the EVP will automatically execute M30, AK14 initialization routines, which preset all the Control and Status Registers to their default power-up values. Each reset pin controls a single processor. A user can connect all of them together if required. C6,V27,B5,AG5, Receive PCM Signal Inputs (Inputs). Port 1 TDM AH6,U28,B27,B28, data input streams. Each Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per D13 stream. C7,U30,B6,AG7, Send PCM Signal Inputs (Inputs). Port 2 TDM data AG6,U29,B30,C27, input streams. Each Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. A12 A5,V30,A6,AH7, Receive PCM Signal Outputs (Outputs). Port 2 TDM AG8,V28,C26,C30, data output streams. Each Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per C13 stream. Rin1, Rin2, Rin3, Rin4, Rin5, Rin6, Rin7, Rin8, Rin9 Sin1, Sin2, Sin3, Sin4, Sin5, Sin6, Sin7, Sin8, Sin9 Rout1, Rout2, Rout3, Rout4, Rout5, Rout6, Rout7, Rout8, Rout9 User Signals User Signals User Signals Zarlink Semiconductor Inc. 5 ZL50212 Signal Name Sout1,Sout2,Sout3, Sout4,Sout5,Sout6, Sout7,Sout8,Sout9 Signal Type User Signals BGA Ball # Signal Description Data Sheet B7,W27,A7,AH8, Send PCM Signal Outputs (Outputs). Port 1 TDM AF9,W30,C29,D30, data output streams. Each Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per B13 stream. K29 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. This signal is connected to all processors. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. This signal is connected to all processors. DS User Signal User Signal User Signals M29 R/W DTA1, DTA2, DTA3, DTA4, DTA5, DTA6, DTA7, DTA8, DTA9 N2,AK28,N1,AK6, Data Transfer Acknowledgment (Open Drain AJ7,AK27,M28, Output). These active low outputs indicate that a data bus transfer is completed. A pull-up resistor (1K M27,AK16 typical) is required at these outputs. V29 Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout ST-BUS outputs are high impedance. This signal is connected to all processors. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications.This signal is connected to all processors. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout).This signal is connected to all processors. Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 20MHz Master Clock input must be applied. When Fsel pin is high, nominal 10MHz Master Clock input must be applied.This signal is connected to all processors. Master Clock (Input). Nominal 10MHz or 20MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source.This signal is connected to all processors. User Signal ODE User Signal F0i B26 C4i User Signal User Signal B25 A15 Fsel MCLK User Signal A16 IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ8, IRQ9 User Signals N4,AJ26,N3,AK5, Interrupt Request (Open Drain Output). These AJ6,AG23,L30,L29, outputs go low when an interrupt occurs in any channel. Each IRQ returns high when all the interrupts AK15 have been read from the Interrupt FIFO Register of respective EVP. A pull-up resistor (1K typical) is required at these outputs. 6 Zarlink Semiconductor Inc. Data Sheet Signal Name Signal Type Extra Device Pins BGA Ball # Signal Description ZL50212 W3,E15,V4,AK16, No connection. The ball pins must be left open for AK15,AK14,D13, normal operation. C13,V3,A12,B13, AK13,AH14,U3,V2, AJ14 JTAG SIGNAL PINS K2 TMS JTAG Signal JTAG Signal D6 Test Mode Select (3.3V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. This signal is connected to all processors. Test Clock (3.3V Input). Provides the clock to the JTAG test logic.This signal is connected to all processors. Test Reset (3.3V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that all the EVP's are in the normal functional mode. This pin is pulled by an internal pull-down when not driven. This signal is connected to all EVP's. TCK D7 TRST JTAG Signal TDI1,TDI2,TDI3,TDI4, TDI5,TDI6,TDI7,TDI8, TDI9 TDO1,TDO2,TDO3, TDO4,TDO5,TDO6 TDO7,TDO8,TDO9 JTAG Signals K1,AK23,L2,AK2, Test Serial Data In (3.3V Input). JTAG serial test AJ3,AH20,F27, instructions and data are shifted in on these pins. H27, AK13 These pins are pulled high by an internal pull-up when not driven. L1,AJ22,L4,AH4, AK3,AK24,J28, K28,AH14 Test Serial Data Out (Output). JTAG serial data is output on this pins on the falling edge of TCK. These pins are held in high impedance state when JTAG scan is not enabled. JTAG Signals PLL SIGNAL PINS PLLVDD2 = 1.8V PLL Power H3,V1,H4,AE3, AG2,AE26,D22, C24, AE27 PLL Power Supply. Must be connected to VDD2 = 1.8V. PLLVSS1 PLLVSS2 PLL Power J3,W2,H2,AF4, PLL Ground. Must be connected to VSS. AF3,AF27,D24, C25,AF26,H1,W4, J2, AH1,AG3,AF22, D25,E27,AF21 D1,AH26,E1,AE1, Internal Connection. Connected to VSS for normal AD4,AK22,D18, operation. C18,U3 F2,AG25,G3,AF1, Internal Connection. Connected to VSS for normal AD3,AF25,B18, operation. A18,V2 T1M1, T1M2, T1M3, T1M4, T1M5, T1M6, T1M7, T1M8, T1M9 T2M1, T2M2, T2M3, T2M4, T2M5, T2M6, T2M7, T2M8,T2M8 PLL Test Signals PLL Test Signals Zarlink Semiconductor Inc. 7 ZL50212 Signal Name SG1, SG2, SG3, SG4, SG5, SG6, SG7, SG8, SG9 DT1, DT2, DT3, DT4, DT5, DT6, DT7, DT8,DT9 Signal Type PLL Test Signals PLL Test Signals BGA Ball # Signal Description Data Sheet G4,AJ25,F1,AE2, Internal Connection. Connected to VSS for normal AG1,AH25,B17, operation. C17,V3 G2,AF23,G1,AF2, No connection. These pins must be left open for AE4,AJ24,D17, normal operation. A17,V4 K4,AJ20,J1, AH2,AJ1,AG20, F28,F26,W3 No connection. These pins must be left open for normal operation. AT1, AT2, AT3, AT4, PLL Test AT5, AT6, AT7, AT8,AT9 Signals The following description applies to a single EVP (Echo Voice Processor). Note that the ZL5012 contains nine EVP's. 8 Zarlink Semiconductor Inc. Data Sheet 1.0 Single Echo Voice Processor (EVP) Description ZL50212 Each single Echo Voice Processor (EVP) contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A (ECA) and Echo Canceller B (ECB). Each group can be configured in Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64ms echo cancellation. Each Echo Voice Processor contains the following main elements (see Figure 4). * Adaptive Filter for estimating the echo channel * Subtractor for cancelling the echo * Double-Talk detector for disabling the filter adaptation during periods of double-talk * Path Change detector for fast reconvergence on major echo path changes * Instability Detector to combat instability in very low ERL environments * Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection * Disable Tone Detectors for detecting valid disable tones at send and receive path inputs * Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals * Offset Null filters for removing the DC component in PCM channels * 0 to -12dB level adjusters at all signal ports * Parallel controller interface compatible with Motorola microcontrollers * PCM encoder/decoder compatible with /A-Law ITU-T G.711 or Sign-Magnitude coding Each echo canceller in the EVP has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. Sin (channel N) /A-Law/ Linear 0 to -12dB Level Adjust Disable Tone Detector Offset Null Adaptive Filter Non-Linear Processor 0 to -12dB Level Adjust Linear/ /A-Law Sout (channel N) Control Microprocessor Interface Double - Talk Detector MuteR MuteS Path Change Detector Disable Tone Detector /A-Law/ Linear ST-BUS PORT2 Instability Detector ST-BUS PORT1 Narrow-Band Detector Linear/ /A-Law 0 to -12dB Level Adjust 0 to -12dB Level Adjust Rout (channel N) Offset Null Rin (channel N) Echo Canceller (N), where 0 < N < 31 Programmable Bypass Figure 4 - Functional Block Diagram of an Echo Canceller Zarlink Semiconductor Inc. 9 ZL50212 1.1 Adaptive Filter Data Sheet The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to-Back configuration, the first section is used in the receive direction and the second section is used in the transmit direction for the same channel. 2.0 Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition: Lsin > Lrin + 20log10(DTDT) where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0. A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero, adaptation is halted completely. In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the DTDT is set internally to 0.5625 (-5 dB). In some applications the return loss can be higher or lower than 6 dB. The EVP allows the user to change the detection threshold to suit each application's need. This threshold can be set by writing the desired threshold value into the DTDT register. The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: DTDT(hex) = hex(DTDT(dec) * 32768) where 0 < DTDT(dec) < 1 Example: For DTDT = 0.5625 (-5 dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800hex 2.1 Path Change Detector Integrated into the EVP is a Path Change Detector. This permits fast reconvergence when a major change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to "1". An optional path clearing feature can be enabled by setting the PathClr bit in Control Register 3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change. 10 Zarlink Semiconductor Inc. Data Sheet 2.2 Non-Linear Processor (NLP) ZL50212 After echo cancellation, there is always a small amount of residual echo which may still be audible. The EVP uses Zarlink's patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the following equation: TSUP = Lrin + 20log10(NLPTHR) where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: NLPTHR(hex) = hex(NLPTHR(dec) * 32768) where 0 < NLPTHR(dec) < 1 When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP. The NLP processor can be disabled by setting the NLPDis bit to "1" in Control Register 2. The comfort noise injector can be disabled by setting the INJDis bit to "1" in Control Register 1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled. The patented Advanced NLP provides a number of new and improved features over the original NLP found in previous generation devices. The differences between the Advanced NLP and the original NLP are summarized in Table 1. Feature NLP Selection Reject uncanceled echo as noise Reject double-talk as noise Noise level estimator ramping scheme Noise level ramping rate Noise level scaling Register or Bit(s) NLPSel (Control Register 3) NLRun1 (Control Register 3) NLRun2 (Control Register 3) InjCtrl (Control Register 3) NLInc (Noise Control) Noise Scaling Advanced NLP Default Value 1 1 1 1 5(hex) 16(hex) Original NLP Default Value 0 (feature not supported) 0 (feature not supported) 0 (feature not supported) 0 (feature not supported) C(hex) 74(hex) Table 1 - Comparison of NLP Types The NLPSel bit in Control Register 3 selects which NLP is used. A "1" will select the Advanced NLP, "0" selects the original NLP. The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3 Zarlink Semiconductor Inc. 11 ZL50212 selects the ramping scheme. Data Sheet The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid. The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences in the noise estimator operation, the Advanced NLP requires a different scaling value than the original NLP. IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant values. Changing these values may result in undesirable comfort noise performance! The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for background noise. These features were not present in the original NLP. They can be disabled by setting the NLRun1 and NLRun2 bits in Control Register 3 to "0". 2.3 Disable Tone Detector The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (21Hz) sine wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees ( 25 degrees) every 450 ms (25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will trigger. The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between 0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone Detector will trigger. Each EVP has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section. Rin Sin Tone Tone Detector Detector Echo Canceller A ECA Status reg TD bit Rin Sin Tone Tone Detector Detector Echo Canceller B ECB Status reg TD bit Figure 5 - Disable Tone Detection Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is generated (i.e. IRQ pin low). The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per channel basis. When the PHDis bit is set to "1", G.164 tone disable requirements are selected. 12 Zarlink Semiconductor Inc. Data Sheet ZL50212 In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. 2.4 Instability Detector In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability problems in the Adaptive Filter. This instability can result in variable pitched ringing or oscillation. Should this ringing occur, the Instability Detector will activate and suppress the oscillations. The Instability Detector is activated by setting the RingClr bit in Control Register 3 to "1". 2.5 Narrow Band Signal Detector (NBSD) Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo. The NBSD will be active regardless of the EVP functional state. However the NBSD can be disabled by setting the NBDis bit to "1" in Control Register 2. 2.6 Offset Null Filter Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC component, each EVP incorporates Offset Null filters in both Rin and Sin inputs. The offset null filters can be disabled by setting the HPFDis bit to "1" in Control Register 2. 2.7 Adjustable Level Pads The EVP provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from 0 to -12 dB level, in 3 dB steps. Level values are set using the Gains register. CAUTION: Gain adjustment can help interface the ZL5012 to a particular system in order to provide optimum echo cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels and slow convergence. Exercise great care when adjusting these values. The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of attenuation at Rin, and override the values in the Gains register. 2.8 ITU-T G.168 Compliance The ZL5012 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. The ZL5012 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL5012 was classified as "carrier grade" echo canceller. 3.0 EVP Configuration Zarlink Semiconductor Inc. 13 ZL50212 Data Sheet The EVP architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8. 3.1 Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously. Sin echo path A channel A + Adaptive Filter (64ms) channel A Sout Rout PORT2 ECA channel B + echo path B channel B Adaptive Filter (64ms) Rin PORT1 ECB Figure 6 - Normal Device Configuration (64ms) 3.2 Back-to-Back Configuration In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Sin echo path + Adaptive Filter (64ms) - Sout echo path Adaptive Filter (64ms) Rout PORT2 ECA + ECB Rin PORT1 Figure 7 - Back-to-Back Device Configuration (64ms) Back-to-Back configuration is selected by writing a "1" into the BBM bit of Control Register 1 for both Echo Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 cancellers that can 14 Zarlink Semiconductor Inc. Data Sheet be configured into Back-to-Back. ZL50212 Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. 3.3 Extended Delay configuration In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains quiet code. Sin echo path A channel A + Adaptive Filter (128 ms) channel A Rin PORT1 ECA Sout Rout PORT2 Figure 8 - Extended Delay Configuration (128ms) Extended Delay configuration is selected by writing a "1" into the ExtDl bit in Echo Canceller A, Control Register 1. For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control Register 1, Bit 0 must always be set to zero. Table 4 shows the 16 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity. Zarlink Semiconductor Inc. 15 ZL50212 4.0 Echo Canceller Functional States Data Sheet Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. 4.1 Mute In Normal and in Extended Delay configurations, writing a "1" into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a "1" into the MuteS bit replaces the Sout PCM data with quiet code. LINEAR SIGN/ 16 bits MAGNITUDE 2's -Law complement A-Law +Zero (quiet code) 0000hex 80hex CCITT (G.711) -Law FFhex A-Law D5hex Table 2 - Quiet PCM Code Assignment In Back-to-Back configuration, writing a "1" into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a "1" into the MuteS bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Sout. In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be "0". Refer to Figure 4 and to Control Register 2 for bit description. 4.2 Bypass The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame (125 s) in order to properly clear the filter. 4.3 Disable Adaptation When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, the echo canceller continues to cancel echo. 4.4 Enable Adaptation In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state. The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the EVP Registers Description for details. 16 Zarlink Semiconductor Inc. Data Sheet 5.0 Echo Voice Processor (EVP) Throughput Delay ZL50212 The throughput delay of the EVP varies according to the device configuration. For all device configurations, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames. 6.0 Serial PCM I/O channels There are four TDM I/O streams, each with channels numbered from 0 to 31. One input stream is for Receive (Rin) channels, and the other input stream is for Send (Sin) channels. Likewise, two output streams is for Rout PCM channels, and Sout PCM channels. See Figure 9 for channel allocation. 6.1 Serial Data Interface Timing The ZL5012 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way into the bit cell (See Figure 11). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 12). 125 sec F0i ST-BUS F0i GCI interface Rin/Sin Rout/Sout Channel 0 Channel 1 Channel 30 Channel 31 Note: Refer to Figure 11 and Figure 12 for timing details. Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams Zarlink Semiconductor Inc. 17 ZL50212 Base Address + MS Byte 0Dhex 0Fhex 11hex 13hex 15hex 17hex 19hex 1Bhex 1Dhex 1Fhex LS Byte 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex 0Ahex 0Bhex 0Chex 0Ehex 10hex 12hex 14hex 16hex 18hex 1Ahex 1Chex 1Ehex Control Reg 1 Control Reg 2 Status Reg Reserved Flat Delay Reg Reserved Decay Step Size Reg Decay Step Number Control Reg 3 Control Reg 4 Noise Scaling Noise Control Rin Peak Detect Reg Sin Peak Detect Reg Error Peak Detect Reg Reserved DTDT Reg Reserved NLPTHR Step Size, MU Gains Reserved Base Address + MS Byte 2Dhex 2Fhex 31hex 33hex 35hex 37hex 39hex 3Bhex 3Dhex 3Fhex LS Byte 20hex 21hex 22hex 23hex 24hex 25hex 26hex 27hex 28hex 29hex 2Ahex 2Bhex 2Chex 2Ehex 30hex 32hex 34hex 36hex 38hex 3Ahex 3Chex 3Ehex Control Reg 1 Control Reg 2 Status Reg Reserved Flat Delay Reg Reserved Data Sheet Echo Canceller A Echo Canceller B Decay Step Size Reg Decay Step Number Control Reg 3 Control Reg 4 Noise Scaling Noise Control Rin Peak Detect Reg Sin Peak Detect Reg Error Peak Detect Reg Reserved DTDT Reg Reserved NLPTHR Step Size, MU Gains Reserved Table 3 - Memory Mapping of Per Channel Control and Status Registers 18 Zarlink Semiconductor Inc. Data Sheet 7.0 Memory Mapped Control and Status registers ZL50212 Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a "per channel" basis to monitor and control each individual echo canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BFhex and interfaces to PCM channel #5 on all serial PCM I/O streams. As illustrated in Table 3, the "per channel" registers provide independent control and status bits for each echo canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers of the EVP. When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section. Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended Delay or Back-to-Back. 7.1 Normal Configuration For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B, channels 2 and 3 are active. Group 0 1 2 3 4 5 6 7 Channels 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Group 8 9 10 11 12 13 14 15 Channels 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 Table 4 - Group and Channel allocation 7.2 Extended Delay Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5) will carry quiet code. 7.3 Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry quiet code. Zarlink Semiconductor Inc. 19 ZL50212 Group 0 Echo Cancellers Registers Channel 0, ECA Ctrl/Stat Registers Channel 1, ECB Ctrl/Stat Registers 0000h --> 001Fh 0020h --> 003Fh Data Sheet Group 1 Echo Cancellers Registers Channel 2, ECA Ctrl/Stat Registers Channel 3, ECB Ctrl/Stat Registers 0040h --> 005Fh 0060h --> 007Fh Groups 2 --> 14 Echo Cancellers Registers Group 15 Echo Cancellers Registers Channel 30, ECA Ctrl/Stat Registers Channel 31, ECB Ctrl/Stat Registers 03C0h --> 03DFh 03E0h --> 03FFh Main Control Registers <15:0> Interrupt FIFO Register Test Register Reserved Test Register 0400h --> 040Fh 0410h 0411h 0412h ---> FFFFh Figure 10 - Memory Mapping 7.4 Power Up Sequence On power up, the RESET pin must be held low for 100 s. Forcing the RESET pin low will put each EVP in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 s for the PLL to lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups of echo cancellers individually, by writing a "1" into the PWUP bit in each group of echo canceller's Main Control Register. For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3Fhex, to the default power-up value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00hex to Base Address+3Fhex, for the specific application. 7.5 Power management Each group of echo cancellers can be placed in Power Down mode by writing a "0" into the PWUP bit in their respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. The typical power consumption can be calculated with the following equation: PC = 9 * Nb_of_groups + 3.6, in mW where 0 Nb_of_groups 16. 20 Zarlink Semiconductor Inc. Data Sheet 7.6 Call Initialization ZL50212 To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation. Since the Narrow Band Detector is "ON" regardless of the functional state of the Echo Canceller it is recommended that the Echo Cancellers are reset before any call progress tones are applied. 7.7 Interrupts The EVP provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is detected and released. Although each EVP may be configured to react automatically to tone disable status on any input PCM voice channels, the user may want for the external HOST processor to respond to Tone Disable information in an appropriate application-specific manner. Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when a Tone Disable releases. Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory containing the channel number of the echo canceller that has generated the interrupt. All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will toggle low for each pending interrupt. After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address mapping of Status register). The TD bit indicates the presence of a Tone Disable. The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the EVP. To provide more flexibility, the MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section. Zarlink Semiconductor Inc. 21 ZL50212 8.0 JTAG Support Data Sheet The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only. 8.1 Test Access Port (TAP) The TAP provides access to many test functions of the EVP. It consists of four input pins and one output pin. The following pins are found on the TAP. * Test Clock Input (TCK) The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is not driven from an external source. Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD1 when it is not driven from an external source. Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high impedance state. Test Reset (TRST) This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS. * * * * 8.2 Instruction Register In accordance with the IEEE 1149.1 standard, the EVP uses public instructions. The JTAG Interface contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. 8.3 Test Data Registers As specified in IEEE 1149.1, each of the Echo Voice Processor's JTAG Interface contains three test data registers: * Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of each EVP core logic. Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO. Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. * * 22 Zarlink Semiconductor Inc. Data Sheet Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 I/O Supply Voltage (VDD1) Core Supply Voltage (VDD2) Input Voltage Input Voltage on any 5V Tolerant I/O pins Continuous Current at digital outputs Package power dissipation Symbol VDD_IO VDD_CORE VI3 VI5 Io PD Min -0.5 -0.5 VSS - 0.5 VSS - 0.3 Max 5.0 2.5 ZL50212 Units V V V V mA W C VDD1+0.5 7.0 20 3.0 150 7 Storage temperature TS -55 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. . Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated Characteristics 1 2 3 4 5 6 Operating Temperature I/O Supply Voltage (VDD_IO) Core Supply Voltage (VDD_CORE) Input High Voltage on 3.3V tolerant I/O Input High Voltage on 5V tolerant I/O pins Input Low Voltage Sym TOP VDD1 VDD2 VIH3 VIH5 VIL Min -40 3.0 1.6 0.7VDD1 0.7VDD1 3.3 1.8 Typ Max +85 3.6 2.0 VDD1 5.5 0.3VDD1 Units C V V V V V C Typical figures are at 25 and are for design aid only: not guaranteed and not subject to production testing Zarlink Semiconductor Inc. 23 ZL50212 DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Static Supply Current 1 IDD_IO (VDD1 = 3.3V) Single EV Processor IDD_CORE (VDD2 = 1.8V) Single EV Processor 2 3 4 5 I N P U T S Data Sheet Sym ICC IDD_IO IDD_CORE PC VIH VIL IIH/IIL ILU ILD CI VOH VOL IOZ Min Typ 10 65 1.35 Max 250 Units A mA mA W V Test Conditions RESET = 0 32 channels of single EVP are active 32 channels of single EVP are active All EVP's i.e. 288 channels are active Power Consumption Input High Voltage Input Low Voltage Input Leakage Input Leakage on Pullup Input Leakage on Pulldown Input Pin Capacitance 0.7VDD1 0.3VDD1 10 -100 100 10 0.8VDD1 0.4 10 V A A A pF V V A IOH = 12 mA IOL = 12 mA VIN=VSS to 5.5V VIN=VSS to VDD1or 5.5V VIN=VSS VIN=VDD1 6 7 8 9 O U T P U T S Output High Voltage Output Low Voltage High Impedance Leakage 10 Output Pin Capacitance CO 10 pF Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25 VDD1 =3.3V and are for design aid only: not guaranteed and not subject to production testing. C, AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 CMOS Threshold CMOS Rise/Fall Threshold Voltage High Sym VTT VHM Level 0.5VDD1 0.7VDD1 Units V V V Conditions 3 CMOS Rise/Fall Threshold Voltage Low VLM 0.3VDD1 Characteristics are over recommended operating conditions unless otherwise stated AC Electrical Characteristics - Frame Pulse and C4i Characteristic 1 Frame pulse width (ST-BUS, GCI) 2 Frame Pulse Setup time before C4i falling (ST-BUS or GCI) 3 Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) 4 C4i Period 5 C4i Pulse Width High 6 C4i Pulse Width Low 7 C4i Rise/Fall Time Sym tFPW tFPS tFPH tCP tCH tCL tr, tf Min 20 10 10 190 85 85 Typ Max 2* tCP-20 Units ns ns ns ns ns ns ns Notes 122 122 244 150 150 300 150 150 10 Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25 VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing C, 24 Zarlink Semiconductor Inc. Data Sheet ZL50212 AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 2 3 4 Rin/Sin Set-up Time Rin/Sin Hold Time Rout/Sout Delay - Active to Active Output Data Enable (ODE) Delay Sym tSIS tSIH tSOD Min 10 10 Typ Max Units ns ns Test Conditions 60 30 ns ns tODE Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25 VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing C, AC Electrical Characteristics - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated. Characteristic 1 Master Clock Frequency, - Fsel = 0 - Fsel = 1 2 Master Clock Low 3 Master Clock High Sym fMCF0 fMCF1 tMCL tMCH Min 19.0 9.5 20 20 Typ 20.0 10.0 Max 21.0 10.5 Units MHz MHz ns ns Notes Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25 VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing C, AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data delay on read Data hold on read Data setup on write Data hold on write Acknowledgment delay Acknowledgment hold time IRQ delay Sym tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tDHW tAKD tAKH tIRD 0 20 3 0 0 80 8 65 Min 0 0 0 0 0 0 79 15 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25 VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing C, Zarlink Semiconductor Inc. 25 ZL50212 tFPW F0i tFPS C4i tSOD Rout/Sout Bit 0, Channel 31 Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 Data Sheet VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT tSIS Rin/Sin Bit 0, Channel 31 tSIH Bit 6, Channel 0 Bit 5, Channel 0 Bit 7, Channel 0 VTT Figure 11 - ST-BUS Timing at 2.048 Mb/s tFPW F0i tFPS C4i tSOD Sout/Rout Bit 7, Channel 31 Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 VTT tFPH tCP tCH tCL tr VHM VTT VLM tf VTT tSIS Sin/Rin Bit 7, Channel 31 tSIH Bit 1, Channel 0 Bit 2, Channel 0 Bit 0, Channel 0 VTT Figure 12 - GCI Interface Timing at 2.048 Mb/s VTT tODE tODE VTT ODE Sout/Rout HiZ Valid Data HiZ Figure 13 - Output Driver Enable (ODE) tMCH MCLK VTT tMCL Figure 14 - Master Clock 26 Zarlink Semiconductor Inc. Data Sheet DS tCSS CS tRWS R/W tADS A0-A12 VALID ADDRESS ZL50212 VTT tCSH VTT tRWH VTT tADH VTT tDHR VALID READ DATA tDDR D0-D7 READ tDSW D0-D7 WRITE VALID WRITE DATA VTT tDHW VTT tAKH VTT tIRD tAKD DTA IRQ VTT Figure 15 - Motorola Non-Multiplexed Bus Timing Zarlink Semiconductor Inc. 27 ZL50212 9.0 EVP Registers Description Echo Canceller A (ECA): Control Register 1 Power-up 00hex Bit 7 Reset Reset INJDis BBM Bit 6 INJDis Data Sheet R/W Address: 00hex + Base Address Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BBM PAD Bypass AdpDis 0 ExtDI Functional Description of Register Bits When high, the power-up initialization is executed. This presets all register bits including this bit and clears the Adaptive Filter coefficients. When high, the noise injection process is disabled. When low noise injection is enabled. When high, the Back to Back configuration is enabled. When low, the Normal configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same logic value to avoid conflict. When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register controls the signal levels. When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on both Sout and Rout is a function of the echo canceller algorithm. When high, echo canceller adaptation is disabled. The Voice Processor cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics. Bits marked as "1" or "0" are reserved bits and should be written as indicated. When high, Echo Cancellers A and B of the same group are internally cascaded into one 128ms echo canceller. When low, Echo Cancellers A and B of the same group operate independently. PAD Bypass AdpDis 0 ExtDl Echo Canceller B (ECB): Control Register 1 Power-up 02hex Bit 7 Reset Reset INJDis BBM Bit 6 INJDis R/W Address: 20hex + Base Address Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BBM PAD Bypass AdpDis 1 0 Functional Description of Register Bits When high, the power-up initialization is executed which presets all register bits including this bit and clears the Adaptive Filter coefficients. When high, the noise injection process is disabled. When low, noise injection is enabled. When high, the Back to Back configuration is enabled. When low, the Normal configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same logic value to avoid conflict. When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register controls the signal levels. When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on both Sout and Rout is a function of the echo canceller algorithm. When high, echo canceller adaptation is disabled. The Voice Processor cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics. Bits marked as "1" or "0" are reserved bits and should be written as indicated. Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written "0". PAD Bypass AdpDis 1 0 Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one immediately after another. The two writes must be separated by at least 350ns and no more than 20us. 28 Zarlink Semiconductor Inc. Data Sheet Power-up 00hex Bit 7 TDis TDis Bit 6 PHDis Bit 5 NLPDis ZL50212 ECA: Control Register 2 ECB: Control Register 2 Bit 4 AutoTD Bit 3 NBDis Bit 2 HPFDis R/W Address: 01hex + Base Address R/W Address: 21hex + Base Address Bit 1 MuteS Bit 0 MuteR Functional Description of Register Bits When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put into Power Down mode. When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone with periodic phase reversals. When high, the non-linear processor is disabled. When low, the non-linear processors function normally. Useful for G.165 conformance testing. When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones. When low, the echo canceller algorithm will remain operational regardless of the state of the 2100 Hz tone detectors. When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled. When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low, the offset nulling filters are active and will remove DC offsets on PCM input signals. When high, data on Sout is muted to quiet code. When low, Sout carries active code. When high, data on Rout is muted to quiet code. When low, Rout carries active code. PHDis NLPDis AutoTD NBDis HPFDis MuteS MuteR Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one immediately after another. The two writes must be separated by at least 350ns and no more than 20us. Power-up 00hex Bit 7 Reserve Reserve TD DTDet Reserve Reserve Reserve TDG Bit 6 TD ECA: Status Register ECB: Status Register Bit 5 Bit 4 Bit 3 Bit 2 DTDet Reserve Reserve Reserve Functional Description of Register Bits R/W Address: 02hex + Base Address R/W Address: 22hex + Base Address Bit 1 TDG Bit 0 NB Reserved bit. Logic high indicates the presence of a 2100Hz tone. Logic high indicates the presence of a double-talk condition. Reserved bit. Reserved bit. Reserved bit. Tone detection status bit gated with the AutoTD bit (Control Register 2). Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100Hz tone. Logic high indicates the presence of a narrow-band signal on Rin. NB Zarlink Semiconductor Inc. 29 ZL50212 ECA: Flat Delay Register (FD) ECB: Flat Delay Register (FD) Bit 5 FD5 Bit 4 FD4 Bit 3 FD3 Bit 2 FD2 Data Sheet R/W Address: 04hex + Base Address R/W Address: 24hex + Base Address Bit 1 FD1 Bit 0 FD0 Power-up 00hex Bit 7 FD7 Bit 6 FD6 Power-up 00hex Bit 7 NS7 Bit 6 NS6 ECA: Decay Step Number Register (NS) ECB: Decay Step Number Register (NS) Bit 5 NS5 Bit 4 NS4 Bit 3 NS3 Bit 2 NS2 R/W Address: 07hex + Base Address R/W Address: 27hex+ Base Address Bit 1 NS1 Bit 0 NS0 Power-up 00hex Bit 7 0 Bit 6 0 ECA: Decay Step Size Control Register (SSC) ECB: Decay Step Size Control Register (SSC) Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 SSC2 R/W Address: 06hex + Base Address R/W Address: 26hex + Base Address Bit 1 SSC1 Bit 0 SSC0 Note: Bits marked with "0" are reserved bits and should be written "0" Amplitude of MU FIR Filter Length (512 or 1024 taps) 1.0 Step Size (SS) Flat Delay (FD7-0) 2-16 Time Number of Steps (NS7-0) Figure 16 - The MU Profile 30 Zarlink Semiconductor Inc. Data Sheet Functional Description of Register Bits ZL50212 The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one tap is equivalent to 125s (64ms/512 taps). FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The delay is defined as FD7-0 x 8 taps. For example; If FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo canceller FIR filter. The valid range of FD7-0 is: 0 FD7-0 64 in normal mode and 0 FD7-0 128 in extended-delay mode. The default value of FD7-0 is zero. Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is 04hex. Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0. For example; If NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] = 512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps. SSC2-0 NS7-0 Zarlink Semiconductor Inc. 31 ZL50212 ECA: Control Register 3 ECB: Control Register 3 Data Sheet R/W Address: 08hex + Base Address R/W Address: 28hex + Base Address Power-up FBhex Bit 7 NLRun2 NLRun2 InjCtrl NLRun1 RingClr Reserve PathClr Bit 6 InjCtrl Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NLRun1 RingClr Reserve PathClr PathDet NLPSel Functional Description of Register Bits When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. Selects which noise ramping scheme is used. See Table below. When high, the comfort noise level estimator actively rejects uncancelled echo as being background noise. When low, the noise level estimator makes no such distinction. When high, the instability detector is activated. When low, the instability detector is disabled. Reserved bit. Must always be set to one for normal operation. When high, the current echo channel estimate will be cleared and the echo canceller will enter fast convergence mode upon detection of a path change. When low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. Note: this bit is ignored if PathDet is low. When high, the path change detector is activated. When low, the path change detector is disabled. When high, the Advanced NLP is selected. When low, the original NLP is selected. PathDet NLPSel The Table 5 below is the same Table shown on page 11. Advanced NLP Default Value 1 1 1 1 5hex 16hex Feature NLP Selection Reject uncancelled echo as noise Reject double-talk as noise Noise level estimator ramping scheme Noise level ramping rate Noise level scaling Register or Bit(s) NLPSel (Control Register 3) NLRun1 (Control Register 3) NLRun2 (Control Register 3) InjCtrl (Control Register 3) NLInc (Noise Control) Noise Scaling Original NLP Default Value 0 (feature not supported) 0 (feature not supported) 0 (feature not supported) 0 (feature not supported) Chex 74hex Table 5 - Comparison of the NLP Types 32 Zarlink Semiconductor Inc. Data Sheet ECA: Control Register 4 ECB: Control Register 4 ZL50212 R/W Address: 09hex + Base Address R/W Address: 29hex + Base Address Power-up 54hex Bit 7 0 0 SupDec Bit 6 SD2 0 Slow Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SD1 SD0 0 Slow2 Slow1 Slow0 Functional Description of Register Bits Must be set to zero. These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast convergence state following a path change, Reset or Bypass operation. A value of zero will keep the echo canceller in fast convergence indefinitely. Must be set to zero. Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0) For Slow = 1, 2,..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to normal adaptation. For Slow = 0, no adaptation occurs during slow convergence. Power-up 16hex Bit 7 NS7 Bit 6 NS6 ECA: Noise Scaling (NS) ECB: Noise Scaling (NS) Bit 5 NS5 R/W Address: 0Ahex + Base Address R/W Address: 2Ahex + Base Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NS4 NS3 NS2 NS1 NS0 Functional Description of Register Bits This register is used to scale the comfort noise up or down. Larger values will increase the relative level of comfort noise. The default value of 16hex will provide G.168 compliance with the Advanced NLP. A value of 74hex is recommended if the original NLP is used. Power-up 45hex Bit 7 Reserve Reserve NLInc Bit 6 Reserve ECA: Noise Control ECB: Noise Control R/W Address: 0Bhex + Base Address R/W Address: 2Bhex + Base Address Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserve Reserve NLInc3 NLInc2 NLInc1 NLInc0 Functional Description of Register Bits Reserved bits. Must be set to 4hex for normal operation. Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping. When InjCtrl = 0, a higher value will give faster ramping. The default value of 5 hex will provide G.168 compliance with InjCtrl = 1. A value of Chex is recommended if InjCtrl = 0. Zarlink Semiconductor Inc. 33 ZL50212 ECA: Rin Peak Detect Register 2 (RP) ECB: Rin Peak Detect Register 2 (RP) Bit 5 RP13 Bit 4 RP12 Bit 3 RP11 Bit 2 RP10 Data Sheet R/W Address: 0Dhex + Base Address R/W Address: 2Dhex + Base Address Bit 1 RP9 Bit 0 RP8 Power-up N/A Bit 7 RP15 Bit 6 RP14 Power-up N/A ECA: Rin Peak Detect Register 1 (RP) ECB: Rin Peak Detect Register 1 (RP) Bit 4 Bit 3 Bit 2 RP4 RP3 RP2 Functional Description of Register Bits These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Bit 7 RP7 Bit 6 RP6 Bit 5 RP5 R/W Address: 0Chex + Base Address R/W Address: 2Chex + Base Address Bit 1 Bit 0 RP1 RP0 Power-up N/A Bit 7 SP15 Bit 6 SP14 ECA: Sin Peak Detect Register 2 (SP) ECB: Sin Peak Detect Register 2 (SP) Bit 5 SP13 Bit 4 SP12 Bit 3 SP11 Bit 2 SP10 R/W Address: 0Fhex + Base Address R/W Address: 2Fhex + Base Address Bit 1 SP9 Bit 0 SP8 Power-up N/A ECA: Sin Peak Detect Register 1 (SP) ECB: Sin Peak Detect Register 1 (SP) Bit 4 Bit 3 Bit 2 SP4 SP3 SP2 Functional Description of Register Bits These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Bit 7 SP7 Bit 6 SP6 Bit 5 SP5 R/W Address: 0Ehex + Base Address R/W Address: 2Ehex + Base Address Bit 1 Bit 0 SP1 SP0 34 Zarlink Semiconductor Inc. Data Sheet ECA: Error Peak Detect Register 2 (EP) ECB: Error Peak Detect Register 2 (EP) Bit 5 EP13 Bit 4 EP12 Bit 3 EP11 Bit 2 EP10 ZL50212 R/W Address: 11hex + Base Address R/W Address: 31hex + Base Address Bit 1 EP9 Bit 0 EP8 Power-up N/A Bit 7 EP15 Bit 6 EP14 Power-up N/A Bit 7 EP7 Bit 6 EP6 ECA: Error Peak Detect Register 1 (EP) ECB: Error Peak Detect Register 1 (EP) Bit 5 EP5 R/W Address: 10hex + Base Address R/W Address: 30hex + Base Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EP4 EP3 EP2 EP1 EP0 Functional Description of Register Bits These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Power-up 48hex Bit 7 DTDT15 Bit 6 DTDT14 ECA: Double-Talk Detection Threshold Register 2 ECB: Double-Talk Detection Threshold Register 2 Bit 5 DTDT13 Bit 4 DTDT12 Bit 3 DTDT11 Bit 2 DTDT10 R/W Address: 15hex + Base Address R/W Address: 35hex + Base Address Bit 1 DTDT9 Bit 0 DTDT8 Power-up 00hex Bit 7 DTDT7 Bit 6 DTDT6 ECA: Double-Talk Detection Threshold Register 1 ECB: Double-Talk Detection Threshold Register 1 Bit 5 DTDT5 R/W Address: 14hex + Base Address R/W Address: 34hex + Base Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DTDT4 DTDT3 DTDT2 DTDT1 DTDT0 Functional Description of Register Bits This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2's complement linear value defaults to 4800hex= 0.5625 or -5 dB. The maximum value is 7FFFhex = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. Zarlink Semiconductor Inc. 35 ZL50212 ECA: Non-Linear Processor Threshold Register 2 (NLPTHR) ECB: Non-Linear Processor Threshold Register 2 (NLPTHR) Bit 5 NLP13 Bit 4 NLP12 Bit 3 NLP11 Bit 2 NLP10 Data Sheet R/W Address: 19hex + Base Address R/W Address: 39hex + Base Address Bit 1 NLP9 Bit 0 NLP8 Power-up 0Chex Bit 7 NLP15 Bit 6 NLP14 Power-up E0hex Bit 7 NLP7 Bit 6 NLP6 ECA: Non-Linear Processor Threshold Register 1 (NLPTHR) ECB: Non-Linear Processor Threshold Register 1 (NLPTHR) Bit 5 NLP5 R/W Address: 18hex + Base Address R/W Address: 38hex + Base Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NLP4 NLP3 NLP2 NLP1 NLP0 Functional Description of Register Bits This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2's complement linear value defaults to 0CE0hex = 0.1 or -20.0 dB. The maximum value is 7FFFhex = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. Power-up 40hex Bit 7 MU15 Bit 6 MU14 ECA: Adaptation Step Size Register 2 (MU) ECB: Adaptation Step Size Register 2 (MU) Bit 5 MU13 Bit 4 MU12 Bit 3 MU11 Bit 2 MU10 R/W Address: 1Bhex + Base Address R/W Address: 3Bhex + Base Address Bit 1 MU9 Bit 0 MU8 ECA: Adaptation Step Size Register 1 (MU) Power-up 00hex R/W Address: 1Ahex + Base Address R/W Address: 3Ahex + Base Address ECB: Adaptation Step Size Register 1 (MU) Bit 5 MU5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MU4 MU3 MU2 MU1 MU0 Functional Description of Register Bits This register allows the user to program the level of MU. MU is a 16 bit 2's complement value which defaults to 4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1. Bit 7 MU7 Bit 6 MU6 36 Zarlink Semiconductor Inc. Data Sheet ECA: Gains Register 2 ECB: Gains Register 2 Bit 5 Rin1 Bit 4 Rin0 Bit 3 0 Bit 2 Rout2 ZL50212 R/W Address: 1Dhex + Base Address R/W Address: 3Dhex + Base Address Bit 1 Rout1 Bit 0 Rout0 Power-up 44hex Bit 7 0 Bit 6 Rin2 Power-up 44hex Bit 7 0 Bit 6 Sin2 Bit 5 Sin1 ECA: Gains Register 1 ECB: Gains Register 1 R/W Address: 1Chex + Base Address R/W Address: 3Chex + Base Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sin0 0 Sout2 Sout1 Sout0 Functional Description of Register Bits This register is used to select gain values on RIN, ROUT, SIN and SOUT. Gains has the following structure: RIN ROUT SIN SOUT Gains = 0xxx 0xxx 0xxx 0xxx = 0100 0100 0100 0100 (4444hex) default Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above), and has three gain bits. The following table indicates how these gain bits are used: Bit2 1 0 0 0 0 Bit1 Bit0 00 11 10 01 00 Gain Level 0 dB (default) -3 dB -6 dB -9 dB -12 dB Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and will override the settings in Gains. Zarlink Semiconductor Inc. 37 ZL50212 Main Control Register 0 (EC Group 0) Power-up 00hex Bit 7 WR_all Bit 6 ODE R/W Address: 400hex Data Sheet WR_all Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIRQ MTDBI MTDAI Format Law PWUP Functional Description of Register Bits Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000hex to 0003Fhex which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo Cancellers as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main Control Register 0 has the WR_all bit Output Data Enable: This control bit is logically AND'd with the ODE input pin. When both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main Control Register 0 has the ODE bit. Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone Detectors operate as specified in their Echo Canceller B, Control Register 2. When low, the Tone Detectors Interrupts are active. Note: Only the Main Control Register 0 has the MIRQ bit. Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept -Law companded PCM code. Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo canceller A and B execute their initialization routine which presets their registers, Base Address+00hex to Base Address+3Fhex, to the default power up value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. ODE MIRQ MTDBI MTDAI Format Law PWUP 38 Zarlink Semiconductor Inc. Data Sheet Main Control Register 1 (EC Group 1) Main Control Register 2 (EC Group 2) Main Control Register 3 (EC Group 3) Main Control Register 4 (EC Group 4) Main Control Register 5 (EC Group 5) Main Control Register 6 (EC Group 6) Main Control Register 7 (EC Group 7) Main Control Register 8 (EC Group 8) Main Control Register 9 (EC Group 9) Main Control Register 10 (EC Group 10) Main Control Register 11 (EC Group 11) Main Control Register 12 (EC Group 12) Main Control Register 13 (EC Group 13) Main Control Register 14 (EC Group 14) Main Control Register 15 (EC Group 15) Bit 7 Unused Unused MTDBI Bit 6 Unused Power-up 00hex Bit 5 Bit 4 Bit 3 Bit 2 Unused MTDBI MTDAI Format Functional Description of Register Bits ZL50212 R/W Address: 401hex R/W Address: 402hex R/W Address: 403hex R/W Address: 404hex R/W Address: 405hex R/W Address: 406hex R/W Address: 407hex R/W Address: 408hex R/W Address: 409hex R/W Address: 40Ahex R/W Address: 40Bhex R/W Address: 40Chex R/W Address: 40Dhex R/W Address: 40Ehex R/W Address: 40Fhex Bit 1 Law Bit 0 PWUP MTDAI Format Law PWUP Unused Bits. Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM code. A/ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, select -Law companded PCM code. Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo cancellers A and B execute their initialization routine which presets their registers, Base Address+00hex to Base Address+3Fhex, to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. Zarlink Semiconductor Inc. 39 ZL50212 Interrupt FIFO Register Power-up 00hex Bit 7 IRQ IRQ 0 0 I<4:0> Bit 6 0 R/W Address: 410hex Data Sheet Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 I4 I3 I2 I1 I0 Functional Description of Register Bits Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. Unused bit. Always zero. Unused bit. Always zero. I<4:0> binary code indicates the channel number at which a Tone Detector state change has occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated. Test Register Power-up 00hex Bit 7 Reserve Reserve Tirq Bit 6 Reserve R/W Address: 411hex Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserve Reserve Reserve Reserve Reserve Tirq Functional Description of Register Bits Reserved bits. Must always be set to zero for normal operation. Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected. 40 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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